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Low power laser driver design in 28nm CMOS for on-chip and chip-to-chip optical interconnect

This paper discusses the challenges and the trade-offs in the design of laser drivers for very-short distance optical communications. A prototype integrated circuit is designed and fabricated in 28 nm super-low-power CMOS technology. The power consumption of the transmitter is 17.2 mW excluding the VCSEL that in our test has a DC power consumption of 10 mW. The active area of the driver is only 0.0045 mm². The driver can achieve an error-free (<BER < 10^12) electrical data-rate of 25 Gbit/s using a pseudo random bit sequence of 2^7-1. When the driver is connected to the VCSEL module an open optical eye is reported at 15 Gbit/s. In the tested bias point the VCSEL module has a measured bandwidth of 10.7 GHz.

Identiferoai:union.ndltd.org:DRESDEN/oai:qucosa:de:qucosa:34801
Date06 August 2019
CreatorsBelfiore, Guido, Szilagyi, Laszlo, Henker, Ronny, Ellinger, Frank
PublisherSPIE
Source SetsHochschulschriftenserver (HSSS) der SLUB Dresden
LanguageEnglish
Detected LanguageEnglish
Typeinfo:eu-repo/semantics/publishedVersion, doc-type:conferenceObject, info:eu-repo/semantics/conferenceObject, doc-type:Text
Rightsinfo:eu-repo/semantics/openAccess
Relation10.1117/12.2202800, info:eu-repo/grantAgreement/Deutschen Forschungsgemeinschaft/FP7/619197//ADDAPT

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