This thesis considers the real-time implementation phases of a multiple-input multiple-output (MIMO) wireless communication system. The parts which are related to the implementation detail the blocks realized on a field programmable gate array (FPGA) board and define the connections between these blocks and typical radio frequency front-end modules assisting the wireless
communication. Two sides of the implemented communication testbed are discussed separately as the transmitter and the receiver parts. In addition to usual building blocks of the transmitter and the receiver blocks, a special type of iterative parallelized decoding architecture has also been implemented on the testbed to demonstrate its potential in low-latency communication systems. In addition to practical aspects, this thesis also presents theoretical findings for an improved version of the built system using analytical tools and simulation results for possible extensions to orthogonal frequency division multiplexing (OFDM).
| Identifer | oai:union.ndltd.org:METU/oai:etd.lib.metu.edu.tr:http://etd.lib.metu.edu.tr/upload/12608644/index.pdf |
| Date | 01 August 2007 |
| Creators | Aktas, Tugcan |
| Contributors | Yilmaz, Ali Ozgur |
| Publisher | METU |
| Source Sets | Middle East Technical Univ. |
| Language | English |
| Detected Language | English |
| Type | M.S. Thesis |
| Format | text/pdf |
| Rights | To liberate the content for public access |
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