SRAM-based Field Programmable Gate Arrays (FPGAs) must be programmed with configuration data every time they are powered on. In addition to initially programming an FPGA, there are many other applications that require access to FPGA configuration memory such as partial reconfiguration, fault injection, and memory scrubbing. This thesis describes a system that provides high-speed, programmable configuration management for Xilinx FPGAs through external interfaces. This system is an improvement upon the JTAG Configuration Manager (JCM) previously created at BYU. The JCM consists of a custom I/O board paired with a MicroZed development board which includes a Xilinx ZYNQ SoC. This platform is used to implement a flexible configuration management system that can communicate with Xilinx FPGAs at high speeds using the JTAG and SelectMAP interfaces.The improved system described in this thesis increases the maximum data transfer rate of the JCM's JTAG and SelectMAP interfaces and dramatically decreases the processor utilization of user programs running on the JCM. This is accomplished by incorporating a Direct Memory Access (DMA) engine and interrupts into the system. In addition to faster data rates, these changes and the decrease in processor utilization also allow the JCM to manage up to eight JTAG chains simultaneously with the use of a special I/O card.
| Identifer | oai:union.ndltd.org:BGMYU2/oai:scholarsarchive.byu.edu:etd-7886 |
| Date | 01 June 2018 |
| Creators | Zabriskie, Peter William |
| Publisher | BYU ScholarsArchive |
| Source Sets | Brigham Young University |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | Theses and Dissertations |
| Rights | http://lib.byu.edu/about/copyright/ |
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