<p>A found state of the art Continuous Time Sigma Delta ADC is modelled and simulated for the presence of nonidealities. A comparison between two Excess Loop Delay compensation techniques is done, the digital differentiation technique was found to have lower swing at the last integrator, and did not need a gain-bandwidth induced delay sensitive summing amplifier. The detrimental influence of clock jitter is shown. Different DAC linearization techniques are discussed, the DWA algorithm was simulated and found to be the best choice for linearizing the DACs. Through high level modeling in Simulink and verification in the Cadence framework specifications for each building block was determined, a final simulation resulted in a SNDR of 76.3 dB.</p>
| Identifer | oai:union.ndltd.org:UPSALLA/oai:DiVA.org:ntnu-8942 |
| Date | January 2008 |
| Creators | Kaald, Rune |
| Publisher | Norwegian University of Science and Technology, Department of Electronics and Telecommunications, Institutt for elektronikk og telekommunikasjon |
| Source Sets | DiVA Archive at Upsalla University |
| Language | English |
| Detected Language | English |
| Type | Student thesis, text |
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