<p>This report describes the assessment and design of a 10 dBm 2.4 GHz CMOS PA including driver stage. The PA is designed in a 0.18 um CMOS technology. A three stage PA has been designed due to the high voltage gain needed. Class F has been chosen for the output stage. An output filter short-circuiting the second harmonic frequency and reflecting the third harmonic frequency is used to obtain the near-square drain voltage that is characteristic to class F. A lowered supply voltage of 0.9 V is used to avoid exceeding the transistor break-down voltage of 2 V. The typical output power achieved is 10.2 dBm. The drain efficiency of the output stage is 47.7 %, and the PAE of the entire PA is 30.5 %. The final layout excluding bonding pads consumes an area of 0.66 mm2, including four internal inductors consuming a total of 0.59 mm2. The PAE obtained is higher than those of a selection of recently published PAs that are comparable in technology, frequency and output power.</p>
| Identifer | oai:union.ndltd.org:UPSALLA/oai:DiVA.org:ntnu-9317 |
| Date | January 2006 |
| Creators | Kallerud, Torjus Selvén |
| Publisher | Norwegian University of Science and Technology, Department of Electronics and Telecommunications, Institutt for elektronikk og telekommunikasjon |
| Source Sets | DiVA Archive at Upsalla University |
| Language | English |
| Detected Language | English |
| Type | Student thesis, text |
Page generated in 0.0021 seconds