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Low power ASIC design using voltage scaling at the logic level

Mùˆnchen, Techn. University, Diss., 2003.

Identiferoai:union.ndltd.org:OCLC/oai:xtcat.oclc.org:OCLCNo/76692026
Date January 2003
CreatorsMahnke, Torsten.
Publisher[S.l. : s.n.],
Source SetsOCLC
LanguageEnglish
Detected LanguageEnglish
SourceLF

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