The aim of the project is to design a generic logic analyzer based on an FPGA. The analyzer should be able to analyze protocols such as I2C, SPI, RS232, RS485 and GPIO. The captured data can be observed using an embedded graphical display or using a PC. The PC can be used to control the analyzer and to save the captured data. The thesis is divided into several parts. First, the basic structure of the analyzer is described including detailed description of its particular components. Later on, the most common protocols that can be decoded using the analyzer are described. Finally, the FPGA subsystem and microcontroller application are presented together with corresponding source codes.
| Identifer | oai:union.ndltd.org:nusl.cz/oai:invenio.nusl.cz:219959 |
| Date | January 2013 |
| Creators | Tajč, Martin |
| Contributors | Povalač, Karel, Kubíček, Michal |
| Publisher | Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií |
| Source Sets | Czech ETDs |
| Language | Czech |
| Detected Language | English |
| Type | info:eu-repo/semantics/masterThesis |
| Rights | info:eu-repo/semantics/restrictedAccess |
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