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Parallel processor architecture for a digital beacon receiver

A digital beacon receiver has been developed to monitor the OLYMPUS satellite beacons. The receiver accepts a nominal 10 MHz IF input and processes the signal using digital signal processing techniques. Fast Fourier transforms are used to locate the carrier within 0.5 Hz. The outputs of the receiver include the frequency and the power of the carrier. / Master of Science

Identiferoai:union.ndltd.org:VTETD/oai:vtechworks.lib.vt.edu:10919/41422
Date04 March 2009
CreatorsRunyon, Ginger R.
ContributorsElectrical Engineering
PublisherVirginia Tech
Source SetsVirginia Tech Theses and Dissertation
LanguageEnglish
Detected LanguageEnglish
TypeThesis, Text
Formatix, 115 leaves, BTD, application/pdf, application/pdf, application/pdf, application/pdf
RightsIn Copyright, http://rightsstatements.org/vocab/InC/1.0/
RelationOCLC# 22607030, LD5655.V855_1990.R869.pdf, LD5655.V855_1990.R869_drw01a.pdf, LD5655.V855_1990.R869_drw01b.pdf

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