Within the framework of this thesis, the influence of non equilibrium post growth thermal treatments of ion implanted and epitaxially grown Ge1-xSnx and Si1-x-yGeySnx layers for nano and optoelectronic devices has been investigated. The main focus has been placed on the study and development of thermal treatment conditions to improve the as grown layer quality and the fabrication of Ge1-xSnx and Si1-x-yGeySnx on SOI JNTs. In addition, through layer characterization, exhaustive analysis has provided deep insight into key material properties and the alloy´s response to the thermal treatment. For instance, (i) the conversion of as grown in plane compressive strained Ge1-xSnx into in-plane tensile strained Ge1-xSnx after PLA that is required for high mobility n-type transistors and (ii) the evolution of monovacancies to larger vacancy clusters due to post growth thermal treatments. Moreover, the adaption of CMOS compatible fabrication approaches to the novel Ge1-xSnx and Si1-x-yGeySnx alloys allowed the successful fabrication of first lateral n-type JNTs on SOI with remarkable Ion/Ioff ratios of up to 10^8 to benchmark the alloy performance.:I. Table of contents
II. Abstract
III. Kurzfassung (Abstract in German)
IV. List of Abbreviations
V. List of Symbols
VI. List of Figures
VII. List of Tables
1 Introduction
2 Fabrication and properties of Ge1 xSnx and Si1 x yGeySnx alloys
2.1 Alloy formation
2.2 Strain and defects
2.3 Electrical and optical properties
2.3.1 Band structure of strain relaxed alloys
2.3.2 Band structure of strained alloys
2.3.3 Doping influenced properties
2.3.4 Electrical properties
2.4 Thermal treatments
2.4.1 Rapid thermal annealing
2.4.2 Flash lamp annealing
2.4.3 Pulsed laser annealing
2.5 Summary
3 Experimental setups
3.1 Molecular beam epitaxy (MBE)
3.2 Ion beam implantation
3.3 Pulsed laser annealing (PLA)
3.4 Flash lamp annealing (FLA)
3.5 Micro Raman spectroscopy
3.6 Rutherford backscattering spectrometry (RBS)
3.7 X ray diffraction (XRD)
3.8 Secondary ion mass spectrometry (SIMS)
3.9 Hall effect measurement
3.10 Transmission electron microscopy (TEM)
3.11 Positron annihilation spectroscopy (PAS)
3.12 Cleanroom
4 Post growth thermal treatments of Ge1-xSnx alloys
4.1 Post growth pulsed laser annealing
4.1.1 Material fabrication and PLA annealing
4.1.2 Microstructural investigation
4.1.3 Strain relaxation and optical properties
4.1.4 Electrical properties and defect analysis
4.1.5 Strain relaxed Ge1-xSnx as virtual substrates
4.1.6 Conclusion
4.2 Post growth flash lamp annealing
4.2.1 Material fabrication and r FLA annealing
4.2.2 Alloy composition and strain analysis
4.2.3 Defect investigation
4.2.4 Dopant distribution and activation
4.2.5 Conclusion
5 Fabrication of Ge1-xSnx and Si1-x-yGeySnx alloys on SOI
5.1 Alloy fabrication with ion beam implantation and FLA
5.1.1 Si1-x-yGeySnx formation via implantation and FLA
5.1.2 Si1-x-yGeySnx on SOI fabrication via implantation and FLA
5.1.3 Recrystallization of Si1-x-yGeySnx on SOI by FLA
5.1.4 P and Ga doping of Si1 x yGeySnxOI via implantation and FLA
5.1.5 Conclusion
5.2 MBE and post growth thermal treatments of Ge1-xSnx and Si1-x-yGeySnx on SOI
5.2.1 MBE growth of Ge0.94Sn0.06 and Si0.14Ge0.80Sn0.06 on SOI
5.2.2 Microstructure of as grown Ge0.94Sn0.06 and Si0.14Ge0.80Sn0.06
5.2.3 Microstructure after post growth thermal treatments
5.2.4 Dopant concentration and distribution
5.2.5 Conclusion
6 Ge1-xSnx and Si1-x-yGeySnx on SOI junctionless transistors
6.1 Operation principle of n type JLFETs
6.2 Fabrication of n-type JNTs
6.3 Electrical characterization
6.3.1 JNT performance evolution during processing
6.3.2 JNT performance in dependence on post growth PLA
6.3.3 Gate configuration of Ge1-xSnx JNTs
6.3.4 Influence of post fabrication FLA on Ge1-xSnx JNTs
6.4 Conclusion
7 Conclusion and future prospects
References
8 Appendix
8.1 Sample list and fabrication details for Chapter 4
8.2 Extended RBS information
8.3 Extended TEM analysis for section 4.1.2
8.4 Strain calculation based on (224) RSM
8.5 Strain calculation by µ Raman
8.6 Analysis of Hall effect measurements
8.7 VEPFit and ATSUP simulations
8.8 Strain relaxation of Ge0.89Sn0.11 for section 4.1.5
8.9 COMSOL simulation of FLA temperature
8.10 ECV measurement setup
8.11 Datasheet of the SOI wafers
8.12 Sample list of Chapter 5
8.13 Calculation of the ion beam implantation parameter by SRIM
8.14 RBS simulation results for section 5.1
8.15 GI XRD and (224) XRD RSM results for section 5.1
8.16 SIMS limitations for section 5.1.4
8.17 RBS of Ge1-xSnx on SOI for section 5.2.3
8.18 Fit procedure for SOI RSM peak positions
8.19 Supporting µ Raman results for section 5.2.3
8.20 Process details for n-JNT fabrication
8.21 Flat band voltage VFB and on current Ion of JNTs
8.22 Ioff, Imax, Ion/Ioff and Imax/Ioff ratio of JNTs
8.23 Subthreshold swing SS calculation of JNTs
8.24 Threshold voltage Vth of JNTs 187
8.25 Gate configuration of Si1-x-yGeySnx JNTs
8.26 n-type transistors compared in Chapter 7
8.27 Annealing setup description
| Identifer | oai:union.ndltd.org:DRESDEN/oai:qucosa:de:qucosa:92554 |
| Date | 07 August 2024 |
| Creators | Steuer, Oliver |
| Contributors | Prucnal, Slawomir, Georgiev, Yordan, Cuniberti, Gianaurelio, Helm, Manfred, Kornelius, Nielsch, Technische Universität Dresden |
| Source Sets | Hochschulschriftenserver (HSSS) der SLUB Dresden |
| Language | English |
| Detected Language | English |
| Type | info:eu-repo/semantics/publishedVersion, doc-type:doctoralThesis, info:eu-repo/semantics/doctoralThesis, doc-type:Text |
| Rights | info:eu-repo/semantics/openAccess |
| Relation | info:eu-repo/grantAgreement/Bundesministerium für Bildung und Forschung (BMBF)/ForMikro/16ES1075//Group IV heterostructures for high-performance nanoelectronic devices/SiGeSn NanoFETs |
Page generated in 0.0031 seconds