Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering; and, (M.B.A.)--Massachusetts Institute of Technology, Sloan School of Management; in conjunction with the Leaders for Manufacturing Program at MIT, 2009. / Includes bibliographical references (leaves 72-73). / Over the past few years, the Intel Fab-17 facility has aggressively pursued lean methodology to reduce the manufacturing costs associated with its aging 200mm diameter wafer process. One area ripe with improvement opportunities is the processes supplying and managing Test Wafers, which are non-production wafers used to verify production tools and operations. With four test wafer types, hundreds of different sequences of operations (defined as routes), and varying consumption trends, thousands of decisions must be made daily to ensure Test Wafers are available on time and with the proper base characteristics. To further illustrate the magnitude and importance of Test Wafer systems, roughly the same number of Test Wafers are introduced each time period into the fab as production wafers. Through direct observation and process mapping techniques, I identified two system level projects, each containing enormous cost and performance improvements to the entire facility. Project One: Reallocating excess inventory In analyzing the Test Wafer inventory quantity and consumption rates in primary stockroom, I noticed that certain routes had excess inventory while others were deficient, thus leading to significantly more expensive Test Wafers types to be used instead. In order to maximize realized cost savings, I developed a linear optimization program which distributed excess Test Wafer inventory to areas of need. Different re-allocation costs, initial material specifications, and forecasted consumption needs constrained the quantity and location for this redistribution. / (cont.) Per the optimization program's recommendations, I led a team to re-allocate the largest excess Test Wafer inventory area to twelve different locations. The savings for this project correspond to over a year's worth of test wafer inventory now available for these routes and banks. Project Two: Determining supply decisions from a Days of Inventory (DOI) metric The previous process for supplying Test Wafers into the fab was complicated, lacked standardization, required significant human intervention, and led to tool performance impacts despite high operating costs. To address these issues, I designed, developed, and implemented a program which prioritized and calculated thousands of test wafer decisions based upon a Days of Inventory (DOI) metric. By prioritizing actions based on the time until stock out, cost-effective decisions were made while ensuring Test Wafers are available at a tool when needed. The program forecasted short term consumption using an Exponentially Weighted Moving Average (EMWA) and pulled real-time inventory and available Test Wafer material to support the calculations and decision logic. After a successful fab-wide pilot, the "DOI Scheduler" program has now replaced the previous test wafer supply process. As a result, internal fab test wafer inventory will decrease by approximately 35% (as of March 2009, inventory has dropped by 15% and continues downward), Test Wafer availability will improve by approximately 75%, and 4 to 5 hrs a week of labor resources have been saved. / (cont.) Equally important, the prior non-standard process is now standardized, enabling future Test Wafer improvement projects and allowing root cause analysis on previously unsolvable problems. / by David W. Johnson. / M.B.A. / S.M.
| Identifer | oai:union.ndltd.org:MIT/oai:dspace.mit.edu:1721.1/53091 |
| Date | January 2009 |
| Creators | Johnson, David W. (David William), S.M. Massachusetts Institute of Technology |
| Contributors | Deborah Nightingale and Stephen C. Graves., Leaders for Manufacturing Program., Leaders for Manufacturing Program at MIT, Massachusetts Institute of Technology. Department of Mechanical Engineering, Sloan School of Management |
| Publisher | Massachusetts Institute of Technology |
| Source Sets | M.I.T. Theses and Dissertation |
| Language | English |
| Detected Language | English |
| Type | Thesis |
| Format | 88 leaves, application/pdf |
| Rights | M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission., http://dspace.mit.edu/handle/1721.1/7582 |
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