With the advancement of technology, submicron CMOSonly process is available now for
Application Specific Integrated Circuits (ASICs). The high integration leads to the need for
high pin counts. However voltage supply and ground bounce due to many output drivers
switching at the same time is becoming a major problem. In this thesis, a CMOS offchip
buffer design which generates ECL logic levels with lower ground bounce noise is described
and demonstrated. The technique used in designing this buffer to reduce voltage
noise differs from conventional design techniques. Traditionally there are two general
methods to reduce ground bounce. One approach tries to reduce the instantaneous current
change (di/dt) by increasing (prolonging) the rise and fall time of the signals. The other approach
attempts to reduce the parasitic inductance attributed to packaging by using multiple
supply pins. Our technique reduces the voltage noise by controlling the instantaneous current
change through the reduction of current difference during switching time. Based on this
approach, a novel circuit structure is designed. This circuit has a fully symmetrical configuration
and is being selfbiased through negative feedback. A current injection technique is
also used to increase the stability of the circuit. SPICE simulation of the proposed circuit
is performed. Comparison and tradeoffs with other approaches are studied. / Graduation date: 1994
| Identifer | oai:union.ndltd.org:ORGSU/oai:ir.library.oregonstate.edu:1957/37203 |
| Date | 04 August 1993 |
| Creators | Zheng, Jieyin |
| Contributors | Lu, Shih-Lien |
| Source Sets | Oregon State University |
| Language | en_US |
| Detected Language | English |
| Type | Thesis/Dissertation |
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