The first topic of this thesis is to propose a design of an all-digital low¡Vpower PLL (ADPLL). This design is implemented by only using standard cell library. The design cycle is effectively reduced. Furthermore, the portability and reusability of the proposed design is significantly raised. The large power consumption, glitch hazards, and timing violations of prior ADPLL designs are avoided by the proposed control method and modified DCO with multiplexers. The proposed design is implemented by only using the standard cell library of TSMC (Taiwan Semiconductor Manufacturing Company) 0.18 um 1P6M CMOS process. The feature of power saving is verified by measurement, which shows that the power consumption of the proposed ADPLL is merely 1.45 mW at 166 MHz output.
The second topic of this thesis is a load shift keying wireless modulator circuit for implantable biomedical SOC. We successfully realize data and power transmission between outer controller and an implantable chip via wireless RF transmission interface. The convenience and the safety of using the implantable biomedical chip are significantly improved. The proposed on-chip LSK modulator consumes less power and area than those of traditional designs. Hence, the design margin of the implantable biomedical chip will be relaxed. The proposed LSK modulator is implemented with TSMC 0.35um 2P4M mixed-signal process. The proposed wireless RF transmission interface is implemented on PCB with discrete components.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0704106-154055 |
| Date | 04 July 2006 |
| Creators | Tseng, Sheng-lun |
| Contributors | none, none, Chua-chin Wang, none |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0704106-154055 |
| Rights | not_available, Copyright information available at source archive |
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