A high throughput scalable decoder architecture, a tiling approach to reduce the
complexity of the scalable architecture, and two low power decoding schemes have been
proposed in this research. The proposed scalable design is generated from a serial
architecture by scaling the combinational logic; memory partitioning and constructing a
novel H matrix to make parallelization possible. The scalable architecture achieves a high
throughput for higher values of the parallelization factor M. The switch logic used to
route the bit nodes to the appropriate checks is an important constituent of the scalable
architecture and its complexity is high with higher M. The proposed tiling approach is
applied to the scalable architecture to simplify the switch logic and reduce gate
complexity.
The tiling approach generates patterns that are used to construct the H matrix by
repeating a fixed number of those generated patterns. The advantages of the proposed
approach are two-fold. First, the information stored about the H matrix is reduced by onethird.
Second, the switch logic of the scalable architecture is simplified. The H matrix information is also embedded in the switch and no external memory is needed to store the
H matrix.
Scalable architecture and tiling approach are proposed at the architectural level of the
LDPC decoder. We propose two low power decoding schemes that take advantage of the
distribution of errors in the received packets. Both schemes use a hard iteration after a
fixed number of soft iterations. The dynamic scheme performs X soft iterations, then a
parity checker cHT that computes the number of parity checks in error. Based on cHT
value, the decoder decides on performing either soft iterations or a hard iteration. The
advantage of the hard iteration is so significant that the second low power scheme
performs a fixed number of iterations followed by a hard iteration. To compensate the bit
error rate performance, the number of soft iterations in this case is higher than that of
those performed before cHT in the first scheme.
| Identifer | oai:union.ndltd.org:tamu.edu/oai:repository.tamu.edu:1969.1/2529 |
| Date | 01 November 2005 |
| Creators | Selvarathinam, Anand Manivannan |
| Contributors | Choi, Gwan |
| Publisher | Texas A&M University |
| Source Sets | Texas A and M University |
| Language | en_US |
| Detected Language | English |
| Type | Book, Thesis, Electronic Dissertation, text |
| Format | 675981 bytes, electronic, application/pdf, born digital |
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