Since the development of SoC is very fast, how to reduce the power consumption of SoC has become a very important issue. To overcome the issue, the hardware circuit provides multi-voltage method to reduce task power consumption. On the other hand, the software tool decides the task voltage to minimize the total power consumption. In this thesis, we developed a genetic algorithm to solve the voltage mapping problem of multi-voltage systems. This goal of this genetic algorithm is to consider the time constraints or power constraints in the multi-voltage system to find the better solution. In order to apply genetic algorithm to solve voltage mapping problem, we build a compilation flow that embeds in the genetic algorithm.
To demonstrate the efficiency of proposed approach, we apply compilation flow to two examples. One is multi-voltage reconfigurable processor system. The processor in the system provides multi-mode and multi-voltage. The multi-mode can reduce the execution time of tasks with high parallelism. Multi-voltage can reduce the power consumption of task by decreasing voltage. We use genetic algorithm to choose task mode to achieve the performance goal. Another is multiple multi-voltage processors. We use list-scheduling to find the task schedule and use genetic algorithm to choose the task voltage. This method can reduce total power consumption. According to the experimental results, the proposed genetic algorithm can reduce the power consumption efficiently.
Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0721106-143740 |
Date | 21 July 2006 |
Creators | Xie, Yao-Ren |
Contributors | Shen-Fu Hsiao, Pei-Yin Chen, Shiann-Rong Kuang, Yun-Nan Chang, Jer-Min Jou |
Publisher | NSYSU |
Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
Language | English |
Detected Language | English |
Type | text |
Format | application/pdf |
Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0721106-143740 |
Rights | unrestricted, Copyright information available at source archive |
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