Jiang, Mingqi. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2009. / Includes bibliographical references (leaves [49]-51). / Abstract also in Chinese. / Abstract --- p.i / Acknowledgement --- p.iii / Chapter 1 --- Introduction --- p.1 / Chapter 2 --- Rewiring Background --- p.4 / Chapter 2.1 --- REWIRE --- p.6 / Chapter 2.2 --- GBAW --- p.7 / Chapter 3 --- Retiming --- p.9 / Chapter 3.1 --- Min-Clock Period Retiming --- p.9 / Chapter 3.2 --- Min-Area Retiming --- p.17 / Chapter 3.3 --- Retiming for Low Power --- p.18 / Chapter 3.4 --- Retiming with Interconnect Delay --- p.22 / Chapter 4 --- Rewired Retiming for Flip-flop Reduction --- p.26 / Chapter 4.1 --- Motivation and Problem Formulation --- p.26 / Chapter 4.2 --- Retiming Indication --- p.29 / Chapter 4.3 --- Target Wire Selection --- p.31 / Chapter 4.4 --- Incremental Placement Update --- p.33 / Chapter 4.5 --- Optimization Flow --- p.36 / Chapter 4.6 --- Experimental Results --- p.38 / Chapter 5 --- Power Analysis for Rewired Retiming --- p.41 / Chapter 5.1 --- Power Model --- p.41 / Chapter 5.2 --- Experimental Results --- p.44 / Chapter 6 --- Conclusion --- p.47 / Bibliography --- p.50
| Identifer | oai:union.ndltd.org:cuhk.edu.hk/oai:cuhk-dr:cuhk_326803 |
| Date | January 2009 |
| Contributors | Jiang, Mingqi., Chinese University of Hong Kong Graduate School. Division of Computer Science and Engineering. |
| Source Sets | The Chinese University of Hong Kong |
| Language | English, Chinese |
| Detected Language | English |
| Type | Text, bibliography |
| Format | print, vi, 51 leaves : ill. ; 30 cm. |
| Rights | Use of this resource is governed by the terms and conditions of the Creative Commons “Attribution-NonCommercial-NoDerivatives 4.0 International” License (http://creativecommons.org/licenses/by-nc-nd/4.0/) |
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