Today the application of the embedded system is more complex. Especially the multimedia function is most popular. But it is still difficult to work smooth on the embedded systems. However, there are some solutions to solve this problem, like DSP and some specific codec chips. But these methods are almost outside of the embedded microprocessor. Here we advance a new architecture, Multimedia Operation Register. We use the bit slice concept to design operation pair which combining bit storage cell and bit computation. Sixty four operation pairs form a MOSU¡]Multimedia Operation Storage Unit¡^. One MOSU could execute all multimedia instructions. We using multiple MOSUs and three register addressing modes to achieve optimal SIMD. The number of MOSUs in Multimedia Operation Register could be determined flexibly by different kinds of operation efficiency requirement.
On the other hand we design new instruction set based on the Intel MMX instruction set and the operation feature of H.26x video codec series. According to the simulation in 6th chapter, new instruction set is more efficient than the Intel MMX instruction set, and the Multimedia Operation Register architecture compared with C64 DSP could obtain 105% performance enhancement.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0726107-144416 |
| Date | 26 July 2007 |
| Creators | Hong, Shou-xi |
| Contributors | Tsung Lee, Chung-Ping Chung, Jih-Ching Chiu, Shen-Fu Hsiao |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726107-144416 |
| Rights | unrestricted, Copyright information available at source archive |
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