Return to search

An automatic test pattern generation in the logic gate level circuits and MOS transistor circuits at Ohio University

No description available.

1. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1183139647

Identifer	oai:union.ndltd.org:OhioLink/oai:etd.ohiolink.edu:ohiou1183139647
Date	January 1986
Creators	Lee, Hoon-Kyeu
Publisher	Ohio University / OhioLINK
Source Sets	Ohiolink ETDs
Language	English
Detected Language	English
Type	text
Source	http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1183139647
Rights	unrestricted, This thesis or dissertation is protected by copyright: all rights reserved. It may not be copied or redistributed beyond the terms of applicable copyright laws.