Aggressive downscaling of complementary metal-oxide-semiconductor (CMOS) transistors has pushed Si-based transistors to their limit. III-V materials have much higher electron mobility compared to Si, which can potentially provide better device performance. Therefore, III-V semiconductor materials have been actively investigated as alternative channel materials, which can extend Moore’s law on CMOS scaling beyond the 22 nm node not only by relying on scaling. Meanwhile, conventional silicon dioxide cannot easily meet the requirement for the scaling of the equivalent oxide thickness; as a result, various high dielectric constant (high-k) materials have been incorporated onto the III-V semiconductor substrate. Nevertheless, the key challenges for high-k/III-V MOSFETs still need to be solved in order to implement high performance high-k/III-V MOSFETs. Those challenges are the lack of high quality and thermodynamically stable insulators that passivate the gate dielectric/III-V interface, compatible III-V p-type MOSFETs, and reliability issue of III-V MOSFETs, etc.
The main focus of this dissertation is to develop proper fabrication processes and structures for III-V MOSFETs devices that result in good interface quality and high device performance. Firstly, we studied the effect of interfacial chemistry on ZrO2/InGaAs gate stack comprehensively, comparing ALD ZrO2 with H2O vs. O3 as the oxidizer. We found that the amount of oxygen is critical to form a good interface. Excessive oxygen concentration, e. g. using O3 as the ALD precursor, induces III-V native oxides at the interface.
The second part of this dissertation focuses on the III-V MOSFETs with various IPLs. Various IPLs have been demonstrated, for example, a thin PVD Si IPL, and ALD Al2O3, HfAlOx, and ZrAlOx. Those IPLs are demonstrated to be effective interfacial dielectric layers to improve device performance, including frequency dispersion, SS, Ion, effective channel mobility, and reliability.
The third part of this study highlights a novel CF4 post-gate plasma treatment on III-V MOSFETs. Fluorine incorporation was demonstrated on various high-k/III-V gate stacks and achieved significant improvements, including Al2O3/In0.53Ga0.47As, Al2O3/InP, HfO2/In0.53Ga0.47As, and HfO2/InP. Detailed physical analysis, electrical characterization and device performance were carried out. With F incorporation, we have successfully developed excellent interface quality of high-k/III-V MOSFETs. As a result, high-performance III-V MOSFETs have been realized.
Finally, emerging non-volatile memories, RRAMs, have been demonstrated. We addressed its conducting mechanism by conducting various experiments and purposed a model for SiOx RRAMs: the conducting filament is randomly formed within the SiOx at the sidewall edge, depending on pre-existing defects. Moreover, the rupture/recovery could occur anywhere along the conducting filament, depending on a random process that determines the location of the weak spot along the conducting filament. In addition, we improved SiO2-based RRAM by incorporating a thin silicon layer onto its sidewall. This technique significantly reduced the electroforming voltage and instability of HRS current of SiO2-based RRAMs. Consequently, a tri-state pulse endurance performance over 106 cycles has been demonstrated and the data stored had good read disturb immunity and thermal disturbance. / text
| Identifer | oai:union.ndltd.org:UTEXAS/oai:repositories.lib.utexas.edu:2152/19623 |
| Date | 26 February 2013 |
| Creators | Chen, Yen-Ting |
| Source Sets | University of Texas |
| Language | en_US |
| Detected Language | English |
| Format | application/pdf |
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