The objective of the thesis is to design and implement in the VHDL language a simple multiprocessor supporting parallel computing. Furthemore, the author has designed and realized universal transparent generic interconnection layer with the objective to connect any given number of processor cores to shared address space using arbitrated bus. Parametrized cache has been allocated to each core in the layer. MSI protocol was used to deal with the issue of memory coherence of the implemented system. Direct and indirect synchornisation support is available to the user. In order to verify the functionality of the system, simple processor core has been designed and implemented, and its copies were connected to the interconnection layer. Various testing programmes have been used to verify the functionality of the system, which also confirmed that the acceleration of computing has been achieved successfully. Virtex6 chip has been used to test the whole system.
| Identifer | oai:union.ndltd.org:nusl.cz/oai:invenio.nusl.cz:235548 |
| Date | January 2010 |
| Creators | Novotný, Jaroslav |
| Contributors | Straka, Martin, Kaštil, Jan |
| Publisher | Vysoké učení technické v Brně. Fakulta informačních technologií |
| Source Sets | Czech ETDs |
| Language | Czech |
| Detected Language | English |
| Type | info:eu-repo/semantics/masterThesis |
| Rights | info:eu-repo/semantics/restrictedAccess |
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