Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2007. / Includes bibliographical references (p. 295-303). / Multilevel copper metallization for Ultra-Large-Scale-Integrated (ULSI) circuits is a critical technology needed to meet performance requirements for advanced interconnect technologies with sub-micron dimensions. It is well known that multilevel topography resulting from pattern dependencies in various processes, especially copper Electrochemical Deposition (ECD) and Chemical-Mechanical Planarization (CMP), is a major problem in interconnects. An integrated pattern dependent chip-scale model for multilevel copper metallization is contributed to help understand and meet dishing and erosion requirements, to optimize the combined plating and polishing process to achieve minimal environmental impact, higher yield and performance, and to enable optimization of layout and dummy fill designs. First, a physics-based chip-scale copper ECD model is developed. By considering copper ion depletion effects, and surface additive adsorption and desorption, the plating model is able to predict the initial topography for subsequent CMP modeling with sufficient accuracy and computational efficiency. Second, a compatible chip-scale CMP modeling is developed. / (cont.) The CMP model integrates contact wear and density-step-height approaches, so that a consistent and coherent chip-scale model framework can be used for copper bulk polishing, copper over-polishing, and barrier layer polishing stages. A variant of this CMP model is developed which explicitly considers the pad topography properties. Finally, ECD and CMP parts are combined into an integrated model applicable to single level and multilevel metallization cases. The integrated multilevel copper metallization model is applied to the co-optimization of the plating and CMP processes. An alternative in-pattern (rather than between-pattern) dummy fill strategy is proposed. The integrated ECD/CMP model is applied to the optimization of the in-pattern fill, to achieve improved ECD uniformity and final post-CMP topography. / by Hong Cai. / Ph.D.
| Identifer | oai:union.ndltd.org:MIT/oai:dspace.mit.edu:1721.1/39551 |
| Date | January 2007 |
| Creators | Cai, Hong, Ph. D. Massachusetts Institute of Technology |
| Contributors | Duane S. Boning and Carl V. Thompson., Massachusetts Institute of Technology. Dept. of Materials Science and Engineering., Massachusetts Institute of Technology. Dept. of Materials Science and Engineering. |
| Publisher | Massachusetts Institute of Technology |
| Source Sets | M.I.T. Theses and Dissertation |
| Language | English |
| Detected Language | English |
| Type | Thesis |
| Format | 303 p., application/pdf |
| Rights | M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission., http://dspace.mit.edu/handle/1721.1/7582 |
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