This work investigates three-dimensional power loop layout for application to a SiC based matrix converter, providing a symmetric, low-inductance solution. The thesis presents various layout types to achieve this design target, and details the implementation of a hybrid layout to the matrix converter phase-leg. This layout is more easily achievable with a surface-mount device package, which also offers benefits such as ease in manufacturing, and a compact package. In order to implement a surface-mount device, a PCB thermal management strategy should be utilized. An evaluation of these methods is also presented in the work. The final power loop solution that implements an aluminum nitride inlay is evaluated through simulated parasitic extraction and experimental double pulse tests. The layout achieves small, symmetric loop inductances. Finally, the full power, three-phase matrix converter demonstrates the successful implementation of this power loop layout. / Master of Science / In the United States, 40% primary energy consumption comes from electricity generation, which is the fastest growing form of end-use energy. Industries such as commercial airlines are increasing their use of electric energy, while phasing out the mechanical and pneumatic aircraft components, as they offer better performance and lower cost. Thus, implementation of high efficiency, electrical system can reduce energy consumption, fuel consumption and carbon emissions [1]. As more systems rely on this electric power, the conversion from one level of power (voltage and current) to another, is critical.
In the quest to develop high efficiency power converters, wide bandgap semiconductor devices are being turned to. These devices, specifically Silicon Carbide (SiC) devices, offer high temperature and high voltage operation that a traditional Silicon (Si) device cannot. Coupled with fast switching transients, these metal oxide semiconductors field effect transistors (MOSFETs), could provide higher levels of efficiency and power density.
This work investigates the benefits of a three-dimensional (3D) printed circuit board (PCB) layout. With this type of layout, a critical parasitic – inductance – can be minimized. As the SiC device can operate at high switching speeds, they incur higher di/dt, and dv/dt slew rates. If trace inductance is not minimal, overshoots and ringing will occur. This can be addressed by stacking PCB traces on top of one another, the induced magnetic field can be reduced. In turn, the system inductance is lowered as well. The reduction of this parameter in the system, reduces the overshoot and ringing.
This particular work applies this technique to a 15kW matrix converter. This converter poses a particular design challenge as there are a large number of devices, which can lead to longer, higher inductance PCB traces. The goal of this work is to minimize the parasitic inductance in this converter for high efficiency, high power density operation.
| Identifer | oai:union.ndltd.org:VTETD/oai:vtechworks.lib.vt.edu:10919/104361 |
| Date | 22 July 2021 |
| Creators | Baker, Victoria Isabelle |
| Contributors | Electrical Engineering, Burgos, Rolando, Dong, Dong, Wen, Bo |
| Publisher | Virginia Tech |
| Source Sets | Virginia Tech Theses and Dissertation |
| Detected Language | English |
| Type | Thesis |
| Format | ETD, application/pdf |
| Rights | In Copyright, http://rightsstatements.org/vocab/InC/1.0/ |
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