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A timing macro model for performance optimization of CMOS logic circuits.

Thesis (M. Eng.)--Carleton University, 1992. / Also available in electronic format on the Internet.

Identiferoai:union.ndltd.org:OCLC/oai:xtcat.oclc.org:OCLCNo/290274052
Date January 1992
CreatorsShum, Roger Chi Fai, Carleton University. Dissertation. Engineering, Electrical.
PublisherOttawa.
Source SetsOCLC
LanguageEnglish
Detected LanguageEnglish
SourceProQuest Full Text

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