A CMOS implementation of a True-Q Flip Flop is presented. It can perform either as
an asynchronous storage element in micropipelines or a part of the synchronizer. It is
capable of double-edge triggering which latches data at both the rising and the trailing
edges. It is also free of the metastability state problem.
Some analog and digital circuits are incorporated with a true double-edge triggered
Flip Flop (DETFF) making it a True-Q Flip Flop. A True-Q Flip Flop outputs an
acknowledge signal only after the Q and NQ are stabilized. Therefore, if the proceeding
stages utilize this acknowledge signal as the triggering signal, then, the value of Q from the
flip flop will not be received by the next stage if Q is in a metastable state.
The number of transistors used in this implementation of True-Q flip flop is 90. Due
to the overhead of circuit complexity, the time delay from Request to Acknowledge signal
is 6.5ns. / Graduation date: 1995
| Identifer | oai:union.ndltd.org:ORGSU/oai:ir.library.oregonstate.edu:1957/35209 |
| Date | 20 October 1994 |
| Creators | Hui, Henry |
| Contributors | Lu, Shih-Lien |
| Source Sets | Oregon State University |
| Language | en_US |
| Detected Language | English |
| Type | Thesis/Dissertation |
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