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Low voltage CMOS digital imaging architecture with device scaling considerations /

Thesis (Ph. D.)--Hong Kong University of Science and Technology, 2004. / Includes bibliographical references (leaves 131-136). Also available in electronic version. Access restricted to campus users.

Identiferoai:union.ndltd.org:OCLC/oai:xtcat.oclc.org:OCLCNo/55889574
Date January 2004
CreatorsXu, Chen.
Source SetsOCLC
LanguageEnglish
Detected LanguageEnglish
SourceView abstract or full-text.

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