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Electroplating bonding technology for chip interconnect, wafer level packaging and interconnect layer structures

Thesis (Ph. D.)--School of Electrical and Computer Engineering, Georgia Institute of Technology, 2004. Directed by Mark G. Allen. / Vita. Includes bibliographical references (leaves 271-284).

Identiferoai:union.ndltd.org:OCLC/oai:xtcat.oclc.org:OCLCNo/54891358
Date January 2003
CreatorsJoung, Yeun-Ho,
Source SetsOCLC
LanguageEnglish
Detected LanguageEnglish
SourceAvailable online, Georgia Institute of Technology, 2004:

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