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Noise Characterization and Modeling of Nanoscale MOSFETs

High-frequency noise modeling and characterization of nanoscale MOSFETs are essential driving forces for highly scaled CMOS technology to be used in radio-frequency applications. Continuous downscaling increases the operating frequency of the MOSFETs, reduces the power supply voltage but does not scale noise accordingly. This makes the noise issue of future low-power technology more prominent and therefore accurate noise modeling more important.
In this thesis, several important issues regarding noise modeling and characterization for nanoscale MOSFETs are studied. First, a new noise factor deembedding algorithm is proposed for on-wafer noise measurements. It solves the problem of noise factor deembedding in which the active two-port device is surrounded by a four-port parasitic network. Based on it, a new deembedding-first and optimization-last noise parameter deembedding approach is proposed and its performance is evaluated using experimental data.
Second, the noise performance of modern sub-100-nm MOSFETs are evaluated using the noise sheet resistance as a figure of merit. It shows that future technologies generally have degraded noise performance. In addition, two accuracy issues regarding the calibration of noise receiver for high-frequency noise measurements are investigated and methods to mitigate these issues are discussed.
Third, a novel Z-parameter based approach to extract the gate resistance is proposed for MOSFET characterization. It is evaluated against other published methods using experimental data. In addition, the extraction of the resistance of the lightly-doped-drain region and the gate contact is also performed and discussed.
Finally, a new perspective to interpret the MSOFET channel noise as suppressed shot noise is presented. An easy-to-use analytical expression for the suppression factor is derived and it only relies on two process parameters – threshold voltage and effective oxide thickness – to predict the level of suppression for the channel noise of MOSFETs. It is evaluated using published experimental data on various CMOS technology nodes. / Thesis / Doctor of Philosophy (PhD)

Identiferoai:union.ndltd.org:mcmaster.ca/oai:macsphere.mcmaster.ca:11375/22004
Date11 1900
CreatorsChen, Xuesong
ContributorsChen, Chih-Hung, Electrical and Computer Engineering
Source SetsMcMaster University
LanguageEnglish
Detected LanguageEnglish
TypeThesis

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