This thesis demonstrate how pipelining in a RISC processor is achieved
by implementing a subset of MIPS R2000 instructions on FPGA.
Pipelining, which is one of the primary concepts to speed up a
microprocessor is emphasized throughout this thesis. Pipelining is
fundamentally invisible for high level programming language user and
this work reveals the internals of microprocessor pipelining and the
potential problems encountered while implementing pipelining. The
comparative and quantitative flow of this thesis allows to understand
why pipelining is preferred instead of other possible implementation
schemes. The methodology for programmable logic development and
the capabilities of programmable logic devices are also given as
background information. This thesis can be the starting point and
reference for programmers who are willing to get familiar with
microprocessors and pipelining.
| Identifer | oai:union.ndltd.org:METU/oai:etd.lib.metu.edu.tr:http://etd.lib.metu.edu.tr/upload/12606778/index.pdf |
| Date | 01 December 2005 |
| Creators | Altinigneli, Muzaffer Can |
| Contributors | Guran, Hasan |
| Publisher | METU |
| Source Sets | Middle East Technical Univ. |
| Language | English |
| Detected Language | English |
| Type | M.S. Thesis |
| Format | text/pdf |
| Rights | To liberate the content for public access |
Page generated in 0.0021 seconds