We outline a multiprocessor architecture that uses modular arithmetic to implement numerical computation with 900 bits of intermediate precision. A proposed prototype, to be implemented with off-the-shelf parts, will perform high-precision arithmetic as fast as some workstations and mini- computers can perform IEEE double-precision arithmetic. We discuss how the structure of modular arithmetic conveniently maps into a simple, pipelined multiprocessor architecture. We present techniques we developed to overcome a few classical drawbacks of modular arithmetic. Our architecture is suitable to and essential for the study of chaotic dynamical systems.
| Identifer | oai:union.ndltd.org:MIT/oai:dspace.mit.edu:1721.1/6021 |
| Date | 01 April 1989 |
| Creators | Wu, Henry M. |
| Source Sets | M.I.T. Theses and Dissertation |
| Language | en_US |
| Detected Language | English |
| Format | 12 p., 2230694 bytes, 827297 bytes, application/postscript, application/pdf |
| Relation | AIM-1119 |
Page generated in 0.0019 seconds