The transition from second-generation (2G) to third-generation (3G) wireless
cellular and cordless telephone systems requires multi-standard adaptability in
a single RF receiver equipment. An important answer to this request is the use of
Delta-Sigma modulators for IF-to-baseband conversion, which will satisfy the dynamic
range requirements for digital signal processing, and at the same time, add
adaptability and programmability to the characteristics of a RF receiver.
This thesis addresses the issues of designing a Delta-Sigma modulator for a
multi-standard wireless receiver. A single-loop third-order modulator topology suitable
for low power and high integration multi-standard receiver design is proposed.
The trade-offs in the modulator design are also presented and explained. The modulator,
which has been implemented as a part of a monolithic receiver chip, will be
fabricated in a standard 0.35-��m CMOS process. The post-layout simulation results
have verified the outcomes of system analysis. / Graduation date: 2004
| Identifer | oai:union.ndltd.org:ORGSU/oai:ir.library.oregonstate.edu:1957/30976 |
| Date | 09 June 2003 |
| Creators | Liu, Mingliang |
| Contributors | Temes, Gabor C. |
| Source Sets | Oregon State University |
| Language | en_US |
| Detected Language | English |
| Type | Thesis/Dissertation |
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