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Design for testability techniques and optimization algorithms for performance and functional testing of mult-chip module interconnections

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Identiferoai:union.ndltd.org:GATECH/oai:smartech.gatech.edu:1853/16635
Date05 1900
CreatorsPendurkar, Rajesh
PublisherGeorgia Institute of Technology
Source SetsGeorgia Tech Electronic Thesis and Dissertation Archive
Detected LanguageEnglish
TypeDissertation
RightsAccess restricted to authorized Georgia Tech users only.

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