As the design of computers advances, two important trends have surfaced: The
exploitation of parallelism and the design against memory latency. Into these two new
trends has come the Multithreaded Virtual Processor (MVP). Based on a standard
superscalar core, the MVP is able to exploit both Instruction Level Parallelism (ILP) and,
utilizing the concepts of multithreading, is able to further exploit Thread Level Parallelism
(TLP) in program code. By combining both hardware and software multithreading
techniques into a new hybrid model, the MVP is able to use fast hardware context
switching techniques along with both hardware and software scheduling. The new hybrid
creates a processor capable of exploiting long memory latency operations to increase
parallelism, while introducing both minimal software overhead and hardware design
changes.
This thesis will explore the MVP model and simulator and provide results that
illustrate MVP's effectiveness and demonstrate its recommendation to be included in future
processor designs. Additionally, the thesis will show that MVP's effectiveness is
governed by four main considerations: (1) The data set size relative to the cache size, (2) the number of hardware contexts/threads supported, (3) the amount of locality within the
data sets, and (4) the amount of exploitable parallelism within the algorithms. / Graduation date: 1999
| Identifer | oai:union.ndltd.org:ORGSU/oai:ir.library.oregonstate.edu:1957/33562 |
| Date | 04 June 1998 |
| Creators | Carlson, Ryan L. |
| Contributors | Lee, Ben |
| Source Sets | Oregon State University |
| Language | en_US |
| Detected Language | English |
| Type | Thesis/Dissertation |
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