This report describes Processor Coupling, a mechanism for controlling multiple ALUs on a single integrated circuit to exploit both instruction-level and inter-thread parallelism. A compiler statically schedules individual threads to discover available intra-thread instruction-level parallelism. The runtime scheduling mechanism interleaves threads, exploiting inter-thread parallelism to maintain high ALU utilization. ALUs are assigned to threads on a cycle byscycle basis, and several threads can be active concurrently. Simulation results show that Processor Coupling performs well both on single threaded and multi-threaded applications. The experiments address the effects of memory latencies, function unit latencies, and communication bandwidth between function units.
| Identifer | oai:union.ndltd.org:MIT/oai:dspace.mit.edu:1721.1/6807 |
| Date | 01 September 1992 |
| Creators | Keckler, Stephen W. |
| Source Sets | M.I.T. Theses and Dissertation |
| Language | en_US |
| Detected Language | English |
| Format | 165 p., 19986107 bytes, 16194697 bytes, application/postscript, application/pdf |
| Relation | AITR-1355 |
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