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Generating efficient layouts from optimized MOS circuit schematics

Donald George Baltus. / Also issued as Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1988. / Includes bibliographical references. / Supported by the U.S. Air Force--Office of Scientific Research. AFOSR-86-0164 Supported in part by a National Science Foundation Graduate Fellowship. Supported in part by Thinking Machines Corporation. 2305/B4

Identiferoai:union.ndltd.org:MIT/oai:dspace.mit.edu:1721.1/4957
Date January 1988
ContributorsBaltus, Donald George.
PublisherResearch Laboratory of Electronics, Massachusetts Institute of Technology
Source SetsM.I.T. Theses and Dissertation
LanguageEnglish
Detected LanguageEnglish
Formatix, 194 p., 10316361 bytes, application/pdf
RelationTechnical report (Massachusetts Institute of Technology. Research Laboratory of Electronics) ; 535.

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