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16-bit Digital Adder Design in 250nm and 64-bit Digital Comparator Design in 90nm CMOS Technologies

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Identiferoai:union.ndltd.org:OhioLink/oai:etd.ohiolink.edu:wright1420674477
Date January 2014
CreatorsBoppana, Naga Venkata Vijaya Krishna
PublisherWright State University / OhioLINK
Source SetsOhiolink ETDs
LanguageEnglish
Detected LanguageEnglish
Typetext
Sourcehttp://rave.ohiolink.edu/etdc/view?acc_num=wright1420674477
Rightsunrestricted, This thesis or dissertation is protected by copyright: some rights reserved. It is licensed for use under a Creative Commons license. Specific terms and permissions are available from this document's record in the OhioLINK ETD Center.

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