The objective of this thesis is to develop circuit-aware interconnect technology
optimization for network-on-chip based many-core architectures. The dimensions of
global interconnects in many-core chips are optimized for maximum bandwidth density
and minimum delay taking into account network-on-chip router latency and size effects
of copper. The optimal dimensions thus obtained are used to characterize different
network-on-chip topologies based on wiring area utilization, maximum core-to-core
channel width, aggregate chip bandwidth and worse case latency. Finally, the advantages
of many-core many-tier chips are evaluated for different network-on-chip topologies.
Area occupied by a router within a core is shown to be the bottleneck to achieve higher
performance in network-on-chip based architectures.
| Identifer | oai:union.ndltd.org:GATECH/oai:smartech.gatech.edu:1853/39632 |
| Date | 02 December 2010 |
| Creators | Balakrishnan, Anant |
| Publisher | Georgia Institute of Technology |
| Source Sets | Georgia Tech Electronic Thesis and Dissertation Archive |
| Detected Language | English |
| Type | Thesis |
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