System-on-chips (SoCs) have become fundamental components in modern electronic devices, from low-power microcontrollers to high-performance AI computing systems. With the increasing demand for performance and efficiency, innovative approaches in power management and clocking mechanisms are increasingly important.
One such approach combines multiple regulator architectures to form a hybrid voltage regulation, which this work demonstrated with buck converters and digital low-dropout (D-LDO) regulators. Additionally, the increasing demand for sub-micro-second voltage scaling in SoCs has pushed regulators to be fully integrated in-package and/or on-chip. Buck converters still offer the highest efficiency compared to other converter topologies but present integration challenges that this work addresses by utilizing a package integrated voltage regulator (PIVR) with full back-end integration of magnetic-core power inductors.
The on-chip D-LDO demonstrated a fully standard cell-based distributed design integrated into an advanced 12nm FinFET process. A focus on reducing excess timing margins has led to a push towards advanced clocking mechanisms like adaptive clocking, which has caused a shift from more traditional PLL-based dynamic voltage and frequency scaling to unified voltage and frequency scaling architectures that use tunable replica oscillators to decrease timing excess timing margins due to voltage droop, process variations, thermals, and aging. This work implemented UVFS with an HVR architecture using a multi-output PIVR cascaded with on-chip D-LDOs and demonstrated it in a complex 22-core network-on-chip SoC in 12nm FinFET.
| Identifer | oai:union.ndltd.org:columbia.edu/oai:academiccommons.columbia.edu:10.7916/atbw-2697 |
| Date | January 2024 |
| Creators | Loscalzo, Erik Jens |
| Source Sets | Columbia University |
| Language | English |
| Detected Language | English |
| Type | Theses |
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