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Selection, Analysis and Implementationof Image-based Feature Extraction Approaches for a Heterogenous, Modular and FPGA-based Architecture for Camera-based Driver Assistance Systems

We propose a scalable and fexible hardware architecture for the extraction of image features, used in conjunction with an attentional cascade classifier for appearance-based object detection. Individual feature processors calculate feature-values in parallel, using parameter-sets and image data that is distributed via BRAM buffers. This approach can provide high utilization- and throughput-rates for a cascade classifier. Unlike previous hardware implementations, we are able to flexibly assign feature processors to either work on a single- or multiple image windows in parallel, depending on the complexity of the current cascade stage. The core of the architecture was implemented in the form of a streaming based FPGA design, and validated in simulation, synthesis, as well as via the use of a Logic Analyser for the verification of the on-chip functionality. For the given implementation, we focused on the design of Haar-like feature processors, but feature processors for a variety of heterogenous feature types, such as Gabor-like features, can also be accomodated by the proposed hardware architecture.

Identiferoai:union.ndltd.org:UPSALLA1/oai:DiVA.org:hh-16377
Date January 2011
CreatorsMühlfellner, Peter
PublisherHögskolan i Halmstad, Intelligenta system (IS-lab)
Source SetsDiVA Archive at Upsalla University
LanguageEnglish
Detected LanguageEnglish
TypeStudent thesis, info:eu-repo/semantics/bachelorThesis, text
Formatapplication/pdf
Rightsinfo:eu-repo/semantics/openAccess

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