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An automatic test pattern generation in the logic gate level circuits and MOS transistor circuits at Ohio University

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Identiferoai:union.ndltd.org:OhioLink/oai:etd.ohiolink.edu:ohiou1183139647
Date January 1986
CreatorsLee, Hoon-Kyeu
PublisherOhio University / OhioLINK
Source SetsOhiolink ETDs
LanguageEnglish
Detected LanguageEnglish
Typetext
Sourcehttp://rave.ohiolink.edu/etdc/view?acc_num=ohiou1183139647
Rightsunrestricted, This thesis or dissertation is protected by copyright: all rights reserved. It may not be copied or redistributed beyond the terms of applicable copyright laws.

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