Recent designs for low-density parity-check (LDPC) codes have exhibited capacity approaching performance for large block length, overtaking the performance of turbo codes. While theoretically impressive, LDPC codes present some challenges for practical implementation. In general, LDPC codes have higher encoding complexity than turbo codes both in terms of computational latency and architecture size. Decoder circuits for LDPC codes have a high routing complexity and thus demand large amounts of circuit area. There has been recent interest in developing analog circuit architectures suitable for decoding. These circuits offer a fast, low-power alternative to the digital approach. Analog decoders also have the potential to be significantly smaller than digital decoders. In this thesis we present a novel and efficient approach to LDPC encoder / decoder (codec) design. We propose a new algorithm which allows the parallel decoder architecture to be reused for iterative encoding. We present a new class of LDPC codes which are iteratively encodable, exhibit good empirical performance, and provide a flexible choice of code length and rate. Combining the analog decoding approach with this new encoding technique, we design a novel time-multiplexed LDPC codec, which switches between analog decode and digital encode modes. In order to achieve this behaviour from a single circuit we have developed mode-switching gates. These logic gates are able to switch between analog (soft) and digital (hard) computation, and represent a fundamental circuit design contribution. Mode-switching gates may also be applied to built-in self-test circuits for analog decoders. Only a small overhead in circuit area is required to transform the analog decoder into a full codec. The encode operation can be performed two orders of magnitude faster than the decode operation, making the circuit suitable for full-duplex applications. Throughput of the codec scales linearly with block size, for both encode and decode operations. The low power and small area requirements of the circuit make it an attractive option for small portable devices.
| Identifer | oai:union.ndltd.org:ADTP/269098 |
| Date | January 2004 |
| Creators | Haley , David |
| Source Sets | Australiasian Digital Theses Program |
| Language | EN-AUS |
| Detected Language | English |
| Rights | Copyright David Haley 2004 |
Page generated in 0.0014 seconds