In this research, a set of integrated I/O interconnection and packaging technologies are investigated. MEMS-based sea-of-leads (SoL) compliant interconnects are demonstrated to be promising to eliminate the need for underfill between a Si chip and organic packaging substrate. Wafer-level packaging with the compliant interconnects can largely reduce the impact on the fragile low-k interlevel dielectric (ILD) films. The technology feasibility of the SoL MEMS I/O interconnects is demonstrated by process integration, assembly, and reliability assessment. To achieve the high power dissipation with compact form factor, integrated thermal-fluidic I/O interconnects and CMOS compatible microchannels are developed to enable a prototype on-chip microfluidic heat sink. In addition, highly integrated electrical and optical interconnects based on dual-mode polymer pillars are fabricated, assembled and tested as a potential solution to the I/O bandwidth bottleneck. The resulting integrated I/O interconnection and packaging technologies are compatible with back-end-of-the-line (BEOL) wafer processing and conventional flip-chip assembly.
| Identifer | oai:union.ndltd.org:GATECH/oai:smartech.gatech.edu:1853/14001 |
| Date | 03 August 2006 |
| Creators | Dang, Bing |
| Publisher | Georgia Institute of Technology |
| Source Sets | Georgia Tech Electronic Thesis and Dissertation Archive |
| Language | en_US |
| Detected Language | English |
| Type | Dissertation |
| Format | 12639079 bytes, application/pdf |
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