In the age of deep submicron VLSI, we can design various system applications in a single chip. On this system-on-chip design, there are ASIC circuitry, processor core together with software components, and hardware modules. During system design, we need to select the forms of execution for kinds of system functions.It is called hardware/software partitioning. Different hardware/software partitioning, affect the achievable cost and performance of the accordingly elaborated system chip designs.
In this research, we explore research and software design issues of an estimation method for hardware/software partitioning. It consists of these tasks:
¡Esoftware scheduling
¡Ehardware/software co-scheduling
¡Ecost and performance estimation for
hardware/software partitioning
For a system description, given a chosen hardware/software partitioning and a set of allocated resources, we can perform the corresponding cost and performance estimation task that can be utilized directly by system designs or can be called by a hardware/software partitioning optimization program. We designed the experimental software for this estimation method. We also carried out a set of experiments based upon real and synthesized design cases.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-1001101-232901 |
| Date | 01 October 2001 |
| Creators | Huang, Yau-Shian |
| Contributors | Chih-Chien Chen, Tsung Lee, Jer-Min Jou |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1001101-232901 |
| Rights | campus_withheld, Copyright information available at source archive |
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