We derive an analytical model for the depletion capacitance of silicon-on-insulator
(SOI) optical modulation diodes. This model accurately describes the parasitic fringe
capacitances due to a lateral pn junction and can be extended to other geometries,
such as vertical and interleaved junctions. Analytical results show excellent agreement
with numerical simulations. The model is used to identify the waveguide slab to rib
height ratio as a key geometric scaling parameter for the modulation e ciency and
bandwidth for lateral diodes. We characterise the fringe capacitance as a parasitic
e ffect that leads to a decrease of about 20% in modulation bandwidth of typical SOI
diodes without a corresponding increase in modulation effi ciency. From the scaling
relations, the most e ffective way to increase the modulation bandwidth is to reduce
the series resistance of the diode. In the light of our analysis, we propose high-speed
and low power microdisk structures for future SOI modulators.
| Identifer | oai:union.ndltd.org:LACETR/oai:collectionscanada.gc.ca:OTU.1807/42970 |
| Date | 28 November 2013 |
| Creators | Jayatilleka, Hasitha |
| Contributors | Poon, Joyce |
| Source Sets | Library and Archives Canada ETDs Repository / Centre d'archives des thèses électroniques de Bibliothèque et Archives Canada |
| Language | en_ca |
| Detected Language | English |
| Type | Thesis |
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