This dissertation explores a few techniques to realize a low-cost monolithic fiber-optic receiver with large-area photo detectors in advanced CMOS processes that could potentially support multi-gigabit digital data across 10 to 20 meters plastic optical fibers (POF). The first techniques investigated in this dissertation are the use of an external pseudo-differential photo detector chip to reduce the impact of the inductive parasitics, and the use of a cross-coupled regulated-cascode (CC-RGC) buffer to relieve the DC voltage headroom issues found in conventional regulated-cascode (RGC) buffers in technologies with low power supply voltages. The second technique investigated in this thesis is the super-Gm transimpedance amplifier (SGM-TIA) that can be used to produce a very small input impedance in order to drive a very large parasitic capacitance exhibited by an integrated photo detector in advanced CMOS processes. The third technique investigated is a linear equalizer with multiple shunt-shunt feedbacks that can be utilized to produce a slowly-rising peaking response in order to compensate for the frequency-dependent losses exhibited by the integrated NW/P-sub photo detector. Two prototype POF receiver test chips have been implemented in TSMC’s 65 nm CMOS processes and non-return-to-zero optical data transmissions have been demonstrated at data rates up to 3.125 Gbps and 4.25 Gbps, respectively, with a 2.5 Gbps grade 670 nm vertical-cavity surface-emitting laser based electro-optical transmitter.
| Identifer | oai:union.ndltd.org:LACETR/oai:collectionscanada.gc.ca:OTU.1807/33978 |
| Date | 11 December 2012 |
| Creators | Dong, Yunzhi |
| Contributors | Martin, Kenneth |
| Source Sets | Library and Archives Canada ETDs Repository / Centre d'archives des thèses électroniques de Bibliothèque et Archives Canada |
| Language | en_ca |
| Detected Language | English |
| Type | Thesis |
Page generated in 0.0016 seconds