An intelligent camera includes a processor, which can extract information from images without the need for an external processing unit, and interface devices used to make the results available to other devices. This paper describes the intelligent camera design and implementation into the Field Programmable Gate Array (FPGA). The implemented architecture contains a camera controller, a memory controller, an IIC controller, a VGA controller, and an execution unit. The camera controller communicates with a CMOS chip. The memory controller communicates with a DDR SDRAM memory. The IIC controller is the interface between a PLB bus and an IIC bus. The VGA controller takes data from the memory and transform them into the VGA format (640x480, 60 Hz). The execution unit extracts the image data from the memory. These data are processed by hardware pixel by pixel, which results in a modified image. The camera units has been implemented in the VHDL and Verilog languages.
| Identifer | oai:union.ndltd.org:nusl.cz/oai:invenio.nusl.cz:217458 |
| Date | January 2008 |
| Creators | Gogol, František |
| Contributors | Macho, Tomáš, Valach, Soběslav |
| Publisher | Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií |
| Source Sets | Czech ETDs |
| Language | Czech |
| Detected Language | English |
| Type | info:eu-repo/semantics/masterThesis |
| Rights | info:eu-repo/semantics/restrictedAccess |
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