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Hardwarové předzpracování paketů pro urychlení síťových aplikací / Hardware Packet Preprocessing for Acceleration of Network Applications

This thesis particularly deals with design and implementation of FPGA unit, which performs hardware acclerated header field extraction of network packets. By utilizing NetCOPE platform it is proposed flexible and effective high-peformance solution for high-speed networks. A theoretical part presents a classical protocol model and an analysis of the Internet traffic. Main part of the thesis is further focused on key issues in hardware packet preprocessing, such as packet classification and deep packet inspection. The author of this thesis also discusses possible technology platforms, which can be utilized to acceleration of network applications.

Identiferoai:union.ndltd.org:nusl.cz/oai:invenio.nusl.cz:236728
CreatorsVondruška, Lukáš
ContributorsMikušek, Petr, Tobola, Jiří
PublisherVysoké učení technické v Brně. Fakulta informačních technologií
Source SetsCzech ETDs
LanguageCzech
Detected LanguageEnglish
Typeinfo:eu-repo/semantics/masterThesis
Rightsinfo:eu-repo/semantics/restrictedAccess

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