The prevalence of multi-core processors in recent years has introduced new
opportunities and challenges to Electronic Design Automation (EDA) research and
development. In this dissertation, a few parallel Very Large Scale Integration (VLSI)
circuit analysis and optimization methods which utilize the multi-core computing
platform to tackle some of the most difficult contemporary Computer-Aided Design
(CAD) problems are presented. The first CAD application that is addressed
in this dissertation is analyzing and optimizing mesh-based clock distribution network.
Mesh-based clock distribution network (also known as clock mesh) is used in
high-performance microprocessor designs as a reliable way of distributing clock signals
to the entire chip. The second CAD application addressed in this dissertation
is the Simulation Program with Integrated Circuit Emphasis (SPICE) like circuit
simulation. SPICE simulation is often regarded as the bottleneck of the design flow.
Recently, parallel circuit simulation has attracted a lot of attention.
The first part of the dissertation discusses circuit analysis techniques. First, a
combination of clock network specific model order reduction algorithm and a port sliding
scheme is presented to tackle the challenges in analyzing large clock meshes with
a large number of clock drivers. Our techniques run much faster than the standard
SPICE simulation and existing model order reduction techniques. They also provide
a basis for the clock mesh optimization. Then, a hierarchical multi-algorithm parallel
circuit simulation (HMAPS) framework is presented as an novel technique of parallel circuit simulation. The inter-algorithm parallelism approach in HMAPS is completely
different from the existing intra-algorithm parallel circuit simulation techniques and
achieves superlinear speedup in practice. The second part of the dissertation talks
about parallel circuit optimization. A modified asynchronous parallel pattern search
(APPS) based method which utilizes the efficient clock mesh simulation techniques for
the clock driver size optimization problem is presented. Our modified APPS method
runs much faster than a continuous optimization method and effectively reduces the
clock skew for all test circuits. The third part of the dissertation describes parallel
performance modeling and optimization of the HMAPS framework. The performance
models and runtime optimization scheme improve the speed of HMAPS further more.
The dynamically adapted HMAPS becomes a complete solution for parallel circuit
simulation.
| Identifer | oai:union.ndltd.org:tamu.edu/oai:repository.tamu.edu:1969.1/ETD-TAMU-2010-12-8597 |
| Date | 2010 December 1900 |
| Creators | Ye, Xiaoji |
| Contributors | Li, Peng |
| Source Sets | Texas A and M University |
| Language | en_US |
| Detected Language | English |
| Type | thesis, text |
| Format | application/pdf |
Page generated in 0.0019 seconds