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A parallel digital interconnect test methodology for multi-chip module substrate networks

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Identiferoai:union.ndltd.org:GATECH/oai:smartech.gatech.edu:1853/13847
Date05 1900
CreatorsNewman, Kimberly Eileen
PublisherGeorgia Institute of Technology
Source SetsGeorgia Tech Electronic Thesis and Dissertation Archive
Languageen_US
Detected LanguageEnglish
TypeDissertation
Format242 bytes, text/html
RightsAccess restricted to authorized Georgia Tech users only.

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