This thesis establishes a quantization noise model of a delta-sigma modulator (DSM), which is utilized to estimate the phase noise performance of a fractional-N frequency synthesizer. In delta-sigma modulator structures, we choose multi-stage noise shaping (MASH) and single-loop structure for investigating the advantages and disadvantages.
We have implemented a 3rd order single-loop and a 3rd order MASH DSM by using Verilog codes and a Xilinx field-programmable gate-array (FPGA). With a reference frequency of 12MHz, the fractional-N frequency synthesizer has an output frequency band of 2400~2500MHz, and a frequency resolution of 183 Hz. The measured phase noise is lower than -54 dBc/Hz at 10 kHz offset frequency. The PLL settling time is less than 29us with a 48 MHz frequency hopping.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0727105-025122 |
| Date | 27 July 2005 |
| Creators | He, Wen-Hau |
| Contributors | Sheng-Fuh Chang, Chin-Chun Meng, Tzong-Lin Wu, Huey-Ru Chuang, Tzyy-Sheng Horng |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0727105-025122 |
| Rights | unrestricted, Copyright information available at source archive |
Page generated in 0.0014 seconds