In the high-speed indoor wireless applications, IEEE 802.11 series is the most dominating LAN standard in the current markets. In this thesis, the design issues of the IEEE 802.11a physical layer baseband system are addressed. Various key modules including Viterbi codec, FFT/IFFT module, OFDM synchronous circuit have been integrated with several other modules to constitute the entire baseband system. This system has been implemented by Verilog HDL and verified against with the C-based behavior model. In addition, it will also be prototyped and optimized on the Altera DSP FPGA Development Board. The transmission of the I, Q channel for the time domain singal is emulated by using the 10-bits AD/DA modules on the FPGA board. The experimental results shows that the gate counts of the transmitter and the receiver are 81,190 and 413,461 respectively.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0907104-165354 |
| Date | 07 September 2004 |
| Creators | Chang, Jia-Jue |
| Contributors | Yun-Nan Chang, Shen-Fu Hsiao, Shiann-Rong Kuang |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0907104-165354 |
| Rights | off_campus_withheld, Copyright information available at source archive |
Page generated in 0.0022 seconds