In today¡¦s modern society, our latest up-to-date technology contains various types of multimedia applications. These applications don¡¦t necessarily have to be executed with the most precise accuracy. In short, they are fault tolerant. As a consequence, this thesis proposes a multi-precision iterative floating-point special function unit, which can be executed under different modes to meet the error requirements of each specific application, and also achieve power reduction during the process.
In order to minimize the area of our design, we have developed two iterative architectures to implement the multi-precision floating point special function unit. The first proposed architecture can perform three kinds of operations, which include a reciprocal operation, a reciprocal square root operation, and last but not least, a logarithm operation. After deciding which function is to be performed, the user can choose four precision modes to execute the special function unit. According to each mode from lowest precision to highest, we name them the first mode, the second mode, the third mode, and the fourth mode. During implementation, a C model has also been designed to evaluate the maximum error of each mode by making comparisons with the most accurate software result, which is the 23 bit result. When the reciprocal function is chosen, and the user defines that application to be performed in full precision, the multi-precision special function operator needs to be executed twice, and it has the error rate of approximately 0.0001%. When less precision is required, we can choose from two intermediate modes, one offers 15 bit accuracy, and the other can guarantee a 12 bit precision. The former precision mode also required the hardware to be executed twice, but the latter only once. The 15 bit accuracy mode has an error rate around 0.01¢H, and the 12 bit mode has the error rate roughly around 0.05¢H. In addition, when visual effects or even audio effects are not our greatest concern, we provide a least accurate mode for the users to pick to execute the special function operator. This mode can maintain 8 bit accuracy, and has the error rate of approximately 0.8%. Other operations including the reciprocal square root, and the logarithm also have four precision modes to choose from. The reciprcocal square root operation can guarantee the same accuracy in each mode as the reciprocal operation, and their error rates are 0.004%, 0.01%, 0.06%, and 0.5% from the highest precision mode to the lowest one. The precisions the logarithm operation can guarantee from highest accuracy to the lowest one are 23, 16, 12, and 8 bits, respectively, and have error rates including 0.00003%, 0.002%, 0.06%, and 0.3%. These different precision choices are built in the proposed structure mainly to reduce the power consumption. The main concept is to pick a low precision mode in order shut down some components in our design. In addition to switching modes, we¡¦ve also added tri-state buffers in certain components as another means to decrease power.
Through experimental results we¡¦ve discovered that the proposed architecture¡¦s affect on power reduction was not as we¡¦ve expected. Due to the integration of the Newton Raphson Method and the Piecewise Polynomial Approximation Method, our architecture¡¦s delay and area have largely increased, and causing a bad influence on saving power. As a consequence, we¡¥ve developed a second architecture to meet our demands. This architecture is mainly based on the Piecewise Polynomial Approximation Method. From this method, we¡¦ve implemented an iterative design which also supports three kinds of operations, the same as the first architecture. It also provides three precision modes for the user to choose. The lowest precision mode provides 8 bit accuracy. The second mode provides 14 bit accuracy, and the third mode, which is the most precise mode, can provide 22 bit accuracy. According to our C model, we can specify our maximum error rate in each function while executing under different modes. When the reciprocal function is executed, the largest error rate in from the lowest mode to the highest mode is 0.19%, 0.00006% and 0.000015% , and the error rate for reciprocal square root from lowest precision mode to the highest is 0.09%, 0.000022% and 0.000014%, and the error rate for the logarithm function is 0.33%, 0.000043% and 0.000015%, from the lowest to the highest. From experimental results we can discover that the newly proposed architecture is better in comparison with the traditional Piecewise Polynomial Approximation architecture. The proposed architecture has a smaller area, and a faster delay, and most important of all, it reduces power and energy affectively.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0907110-214950 |
| Date | 07 September 2010 |
| Creators | Liao, Ying-Chen |
| Contributors | Pei-Yin Chen, Shiann-Rong Kuang, Ren-Der Chen, Yeu-Horng Shiau |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0907110-214950 |
| Rights | not_available, Copyright information available at source archive |
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